[MUSIC] Hello everyone, now we are going to learn our Lecture 11, so far, we've learnt n-channel MOSFET, nMOSFET. N-Channel MOSFET, it has a very high mobility, very high switching element, so the digital array of zero and one, they use the n-channel MOSFET. This week, we're going to learn p-channel MOSFET, p-channel is a lower mobility than n-channel, but p-channel is very important to forming the CMOS, Complementary Metal Oxide Semiconductor. Complementary means, they're using NMOS and PMOS. Using the CMOS, we can build, the various logic devices, including CMOS inverter, CMOS NAND gate, CMOS NOR gate, and we're going to also learn the CMOS logic for inverter. These slides show the p-channel MOSFET, circuit diagram of the PMOS looks like this, And then, almost the same as in MOSFET, but there is a dot at the end of the Gate and also Drain, And the important thing about the PMOS that is to differentiate from the nMOSFET, source, let's say that this is the grounded [COUGH] And then drain is negative voltage or lower voltage compared to the source. And then gate voltage is also negative or lower voltage than source. So everything, the gate and drain voltage is negative compared to the n-MOSFET. So here's the p-MOSFET, and the source and drain and gate. In p-MOSFET, they're using n-type silicon instead of the p-type silicon substrate and the source-drain is the p-pole highly doping instead of the n-pole highly doping n-MOSFET. So, in this PMOS, you are applying negative gate voltage, negative gate voltage and negative drain voltage. If you look at the transfer curve, Id-VG curve, is here, gate, you applying negative gate voltage, negative value and threshold the voltage is also negative. Here, let's assume that threshold the voltage is -0.8 voltage, so threshold, the below voltage, then the threshold voltage, more negative voltage than threshold voltage, transistor will be on. But our own current is also negative voltage and then in here, transport curve is normally measuring at a constant drain voltage. Those constant drain voltage here is negative voltage. This is the Id-Vd curve, the same thing, drain voltage is negative value, -1.0, -2.0, -3.0, and then Id current is negative current, negative, negative negative. And gate voltage is also negative value, more negative value, more negative current is flowing. And around a little above the threshold voltage, a little above the negative threshold voltage which is the negative, they are transistor off. So below the threshold voltage Above the negative threshold voltage, current is off, and the more negative voltage compared to the threshold voltage, transistor on, middle, negative current is flowing. Before we go into the next slide, I would like to emphasize the source, let's say the source is a certain reference of a potential. Then drain voltage and gate voltage should be lower potential than sources. Source can be grounded, sometimes source is not grounded but that they can be a source. Then, drain and gate voltage is lower voltage than source, that is the important thing. As you can see, in this p-channel MOSFET, you need to apply negative gate voltage to form the whole channel between the source and drain, why is that? Let's look at it, the MOS capacitor of the p-channel MOSFET, in p-channel MOSFET, they're using the n-type silicon. So there is a four different thing for the p-channel MOS, electron accumulation, depletion, onset of the inversion, and inversion. So this is opposite to the MOS capacitor of the p-type silicon, so you are applying here positive gate voltage then lowers the potential of the metal side. If you're applying the positive, you Accumulate majority electron in near the oxide layer, majority electron is accumulated, so this is the electron accumulation. If you applying gate voltage just above the threshold voltage and negative voltage, then you increase potential of the gate area. Because the Venn diagram based on the electron, if you're applying negative voltage, you're increasing instead of decreasing. And then, you applying negative gate voltage, you expel the majority electron in silicon or underneath silicon oxide layer, forming the fixed charge. Let's say that this is the n-type silicon, therefore, I seen plus of the fixed charge, they are not moving. If you decreasing more of the gate voltage, where that gate voltage is equal to the negative threshold voltage, then the Fermi energy is below than Ei Or stopping potential is the 2 pi f. Therefore, they are this minority. Holes can be formed underneath silicon oxide layer. Their concentration is equal to the n type silicon doping concentration, but n-type silicon doping concentration is much wider. Let's say the one micron where the minority carrier gathering is less than ten nanometers. So those slight V emergence of the minor carrier is negligible. Much below then threshold, the voltage if gate voltage is much below the threshold the voltage where the transistor of the PMOS is on, huge minority holes is gather just underneath the silicon oxide. Let's say the thickness is ten nanometers. Those are emergent charge. This emergent charge is interestingly can be survived in the measure of the carrier electron in n-type silicon, because those minority carrier hole can be separate with a measure of carrier electron by the fixed depletion charge. Therefore, those depletion layer is important to form hole tenor impeach and are most pen. This most capacitor of the p channel is important. I would like to give you four-minute that you actually practice by yourself to drawing the MOS capacitor of the p channel MOSFET. We learned about the p channel MOSFET. Now, let's learn of the CMOS where the NMOS and PMOS is combined to build various logic circuit. So first, the logic that we learn is the inverter. This is the CMOS inverter. As you can see, there's an n channel MOSFET and p channel MOSFET. So these CMOS inverter is the building block of all integrated circuit, IC. So this inverter actually changing the input signal one to zero and zero to one. So they invert the input signal to out. And then input signal is connected to the gate output and NMOS, and PMOS. And then one end up the PMOS is connected to the BDD and one end of the NMOS is connected to the ground. One end of the PMOS and one end of the NMOS is connected together and dead stop, we out. This NMOS is called a pull-down NMOS and this PMOS called the pull-up PMOS. We're going to learn why they are called pull-down and pull-up in the next two slides. So if you look at the truth table of the inverter is that Vin is the zero througout this one. Vin is the one, then Vout is the zero. Circuit diagram of inverter looks like this, input is inverted. So we are living in a digital era. So controlling one and zero is important. This one is inverting the input signal. And if you look at the Vin, Vout graph if you have, let's say that this V1 is the 2 volts. And then if that is the high one or zero is zero volt, okay? So Vin in high. A Vin equals 0 volt which is 0, then output becomes a 2 volts. That's high. If you input high of one or two volts of the Vin, then output becomes 0, so this is the inverter curve of the Breathe in and breathe out. So why they can do this kind of function? Let's learn in in next slide. So let's say that two volts is the high volt potential. We studied digital one and general voltage is digital zero. Now, you want to changing digital one to digital zero. So input is the two volts digital one as a two volts and then they go to the atmosphere. This is the source of the NMOS and grounded and the let's say the threshold the voltage of NMOS is 0.8 voltage, and threshold the voltage of the PMOS which is the negative is -0.8 voltage. So these NMOS and the PMOS is serially connected from the ground to the VDD two-volt. So depending on the transistor on and off, the resistance is determine if NMOS transistor on resistance of NMOS extremely low. Let's say the 0.0001, if a transistor off of the PMOS, then current on was not flowing means there should be resistance. For easy understanding, if transistor is on, then this resistance is low to the resistance one Ohm. If transistor off, then the resistance of PMOS is very high resistance. Let's say the 100 Ohms for easy understanding. So potential of the Vout should be the between the potential of the zero and two, because this is the two resistance to securely connecting. So potential of the Vout should be lower than VDD. VDD is two volts. This is the lower than the VDD two-volt, but the higher than grounded. So let's look at the PMOS. Inverter, this is the high potential 2V, this is VOUT is the door potential then VDD. So in this PMOS, which one is the source? This one and this one. As I said in PMOS, source is higher voltage than drain. So here is the lower voltage. Therefore, VDD over 2V is source or Reference to the PMOS pair. If 2V becomes the reference, potential is the Reference value. So 0V is compared to the reference 0V, 0V to the 2V, 0V becomes the -2V from the Reference, right? Therefore, you applying the 2V here to the gate of the PMOS, which is the source is the 2V then the effective potential of the gate is 0V instead of the 2V because the Reference is the 2V. So gate of the PMOS is Vin minus Reference of the VDD. Therefore, 2V apply and 2V is Reference to the VDD is the 0V. In PMOS, if you're applying the 0V, transistor off. Therefore this transistor is off. So if you look at the serial connection of resistant, NMOS is transistor on, so low resistance, let's say the 1 Ohm, PMOS is off, high resistance. So what is the potential of the VOUT? If you go back to the general physics, the CDR connection of the low resistance and high resistance, resistant potential in the middle should be proportionally apply. So 1 to 200 ratio. Therefore, potential at the VOUT should be equal to the Ground,. Therefore, this NMOS pair is on, the potential of the VOUT is pulled down by the NMOS becomes the 0V, or 0.02V, the ratio 100 to 1, but this is the 0V. So high potential digital one inverted to the 0V, zero of the digital So digital 1 is inverted to digital 0. So what about the opposite cases? If you're applying 0V in Vin, then 0V becomes the NMOS, is transistor off. 0V to the PMOS because the source and Reference is the 2V if you're applying the 0V, this becomes the -2V. So 2V of the VDD is the Reference. Then if you are applying the 0V it becomes a -2V. Since our threshold of the voltage is -0.8V of the PMOS, if you apply -2V then this PMOS transistor is on. Therefore, resistance is low and resistance over is high. Therefore, output potential becomes the, equal to VDD, therefore, pull up by the PMOS, Therefore, digital 0 is inverted to the digital 1.
