Now we are going to learn short channel effect. As I said previously, channel length becomes lower than the sub-micron regime, there are some different phenomena occur compared to the long channel MOSFET transistor. There are three primary phenomenon called threshold voltage lowering, or it can be called Vth lowering, and threshold voltage deduction. Then drain induced barrier lowering, and subthreshold swing. First, we're going to learn threshold voltage lowering. As channel lengths decreases, threshold voltage becomes lowered. This is bad. Why? Let's think about that you're making billions of transistor from the entire silicon wafer. Then if your threshold voltage is lower than this regime, then channel lengths can be varied a little bit, like 10 percent or 15 percent from the transistor located there, one One the silicon wafer, and the other end of silicon wafer. Then slight change over the channel lengths induced a huge changing of the threshold voltage, then you cannot make a stable IC chip. Some of them is 0.5, some of them 0.7, then our own current is changing because the threshold voltage changing. So this is bad. Then how can you make a better transistor then, even at the short channel regime, the threshold voltage should be constant as it is. That's how the engineer should working on. Then before we learning how to do that, let's learn why this threshold voltage lowering is occur. This is a little complicated, but let me explain it. First, this is the MOSFET transistor gate, source, drain. Then when your transistor on, there is depletion region is formed, and in addition to that, there is electron channel formed between the source and drain by the inversion and the current flowing. The depletion region here is also formed because there is a p-n junction, p-n junction. Another thing you need to know how this inversion is occur. You first applying positive voltage first, so you generating the depletion region of the fixed charge. In here, p-type semiconductor fixed charges, boron minus. Once you form the entirely of the depletion layer, then you form inversion charge. In long-channel device, these shared depleted region is decreasable. Let's say the source to drain channel length is 10 micron, this area is like 20 nanometers. Then 10 micron, 20 nanometer is totally decreasable, and this is our assumption. But what if you making 100 nanometer transistor? Then shared area is 20 nanometer, 20 nanometer. Those 40 nanometers of the channel length is already depleted before you are applying the gate voltage. So you only need to apply the 60 nanometer of the depletion region by applying your gate voltage. So the actual threshold voltage when you forming the inversion charge is hugely reduced because you already depleted, this area is depleted by the p-n junction. Therefore, in short, channel device, threshold the voltage is lower because of the shared charge. So this is the phenomena of why threshold voltage lowering occur when channel length is short. Then how can you prevent them? Because I want a constant threshold voltage in short channel devices. The solution is deducing the depletion region of the p-n junction so that we can deduce the shared area. To deduce depletion region, you need to increase doping labor of the p-type semiconductor. In p-n junction, if you increasing the doping concentration, then depletion with this narrow, you remember the force relationship that I told you? So if you increasing the doping concentration of p-type silicon depletion region is narrow and the shared area narrow; therefore, threshold voltage loading can be prevented. If you increasing the doping concentration of a p-type 10 times, then depletion width can be decreased one over 10, huge decrease. Therefore, as I saying, modern semiconductor transistor, the substrate doping concentration or over is 10 to the 19. That's why they want to deduce the shared depletion region. Drain-deduce barrier lowering is occur when you applying high drain voltage in short-channel devices. These are the long channel device, these are the short channel device. Long channel device, you can think as EC conduction band and then EC, n, p, n, therefore built-in potential of the EC, and then here. So when you applying the low [inaudible] then diagram of the EC of the n, p, n is looks like a built-in potential and audit are lower. In long channel device, even if you are applying the high drain voltage, it's like saying built-in potential and high drain voltage, something like this. The carriers, a lot of carriers electron in source region cannot go over this built-in potential when gate voltage is less than threshold voltage. So transistor is off. Same thing for the short channel device. If drain voltage is low drain voltage, then EC of the source region has a built-in potential, and go down like this, and built-in potential is not changing. Therefore, transistor of current not flowing when gate voltage below the threshold voltage. However, if you applying high drain voltage in short channel device becomes like this because that you don't have enough spacing that those built-in potential is formed. High drain voltage is lower those potential built-in potential barrier because it is short. So therefore, potential built-in potential is reduce, barrier is reduced by the high drain voltage. That's why it call drain-induced barrier loading the IBM. So in this case, even if you're gate voltage is below the threshold voltage, barrier is lower, the carriers can go to the drain region, leakage current flowing, which is the bad, short-term effect. So how to measure DIBL? To measure the DIBL, there's a various way, but one of the ways is measuring the threshold voltage is changing with the high drain voltage of the threshold voltage minus low drain voltage threshold voltage. In long-channel device, threshold voltage doesn't changing whether you are applying high drain voltage, low drain voltage. In short channel device, threshold voltage of a high drain voltage is lower because the huge leakage current is flowing, then current flowing, therefore threshold voltage is lower. Therefore, high Vth over high-drain voltage minus threshold voltage or low voltage becomes the negative, while the long-channel device Delta Vth is zero. That is the DIBL of the short channel devices. What happened in I-V curve? This is the transfer curve, ID versus gate voltage. This is the log's scale instead of the linear scale. Linear scale, I-V curve is like this. In linear scale, you can know the characteristic how much current is flowing. However, in linear scale, you don't know what's going to happen in our off-current, whether transistor is totally off or not or leakage current is flowing or not, because all of the off-current looks like a zero. However, it's not zero. If you look at in a low scale, huge difference. In logs scale, you don't know exactly how much on-current because it's log scale one million, two million pair is almost same in a log scale. But you can find out easily of the op characteristic where the linear current is zero, but they are changing like this. Let's say that these are the own current on threshold voltage. Maybe it can be changing, but here transistor is on, and then threshold voltage is something like this. Then in long tunnel device, op characteristic is steep slope. They can totally turn it up at the gate voltage zero. In short channel device because of DIBL, drain-induced barrier low [inaudible] , because this the drain voltage, two volt. Drain-induced barrier lowering, the potential barrier at the source region is reduced, leakage current is flowing, huge current is flowing here. So [inaudible] op characteristic is bad in short channel device. In this graph, you also can find out the subthreshold swing, which we will learn in next slide. Actually subthreshold swing called SS, and SS and the DIBL is almost a similar phenomenon, but different measuring methodology. Subthreshold swing also tells us how the off-current characteristic, off-current is totally done or that. They measuring the subthreshold swing by Delta V_G over Delta I_D. This means that to turn it up, I_D in one order in log scale, how much voltage is require? Means that if you turn it up 10_10 to 10_11, one order of the current, how much voltage is require? So less voltage is more better. Less voltage is better because you can turn it up one order with the slight changing of the gate voltage. Maybe bad transistor requires a very high voltage, good transistor require very low voltage. You know how much it is? I know it. It's a 60 millivolt per decade Why? Let's run it in the next slide. Subthreshold swing. The definition of SS is how much a gate voltage is needed to increase the drain current one order of magnitude or decrease the drain current one order of magnitude magnetic? Same thing. So measure of the switching, this is the measure of the switching performance, and then SS is 1 over slope. Then in good silicon MOSFET transistor, if you make a good transistor, they are 60 millivolt per decade. If your transistor is the bad characteristic has a 200 millivolts per decade, then there's some room that you can improve of the SS. So large slope is good switching characteristic and small SS value. Also, if you having a derivative of V_G over DI_D, since I_D is like this, this characteristic is 1 over C_ox. Since C_ox has in proportional to the thickness, small thickness, high C_ox. Therefore, thinner oxide has are large C_ox and smaller SS, which is the better. So thinner oxide is better for good of characteristic. In addition to the off characteristic, what about the on-current? On-current is I_D [inaudible] this equation in MOSFET transistor. Also, thinner oxide increasing the C_ox, increasing the on-current. Therefore, high-performance MOSFET transistor, thinner gate oxide is necessary both for on-current and off-current. So modern MOSFET using almost the one nanometers gate silicon oxide thickness to having a high performance MOSFET transistor. Thank you for listening my lecture of semiconductor device. I hope you enjoyed my lecture, and I hope that you understand the semiconductor device, IT technology which will be also very important for the future artificial intelligence and IoT era. We covered a lot of lecture material, but my lecture notes covers very important concept. I recommend you not to go every detail of equation and complicated issue, but the focus on the general concept of semiconductor device using my lecture note. Thank you.
